(i) Field of the Invention
The present invention relates to a resin-sealed semiconductor device with a semiconductor element mounted thereon, a circuit member for use therein and a method of manufacturing a resin-sealed semiconductor device.
(ii) Description of the Related Art
Recently, there has been a tendency (trend) toward the progress of technique for high integration and miniaturization and toward the sophistication and lightening/shortening of electrical equipment. Therefore, semiconductor devices represented by ASIC of LSI have increasingly advanced in high integration and high function. In the highly-integrated and sophisticated semiconductor devices, to process signals at a high speed, the heat developed in chips and the inductance in packages cannot be ignored. To solve the problem, the heat of the chip is allowed to escape from the package by providing a thermal via or the inductance is substantially lowered by increasing the number of power or ground connection terminals. The inductance in the package is reduced in this manner. The high integration and sophistication of the semiconductor devices result in an increase of the number of outer terminals (pins) and further a demand for the provision of multiple terminals (pins).
To meet the demand for multiple terminals (pins), a lead frame is used in the manufacture of a multiple terminal (pin) IC, ASIC especially represented by a gate array or a standard cell, DSP (Digital Signal Processor) or another semiconductor device. Specifically, there is provided a QFP (Quad Flat Package) or another surface mounting type package, and the QFP has even a 300-pin class for practical use.
However, the high speed operation and high performance (function) of the signal processing of a recent semiconductor element require more terminals. In QFP, by narrowing outer terminal pitches, further multiple terminals can be arranged. When the outer terminals have narrow pitches, however, the width of each outer terminal itself needs to be narrowed, thereby lowering an outer terminal strength. As a result, a problem arises in position accuracy or flatness accuracy when the terminals are formed. Furthermore, in QFP, as the outer terminal pitch is further narrowed to 0.3-0.4 mm, a mounting process is complicated, sophisticated board mounting process needs to be realized and another fault (problem) arises.
Moreover, to meet a demand for the miniaturizing/thinning of a sealed type semiconductor device using a lead frame, the trend of development has progressed via the surface mounting type package such as QFP and SOJ (Small Outline J-Leaded Package) to the miniaturization of a package mainly by thinning the package and developing TSOP (Thin Small Outline Package) and further to a structure of LOC (Lead On Chip) obtained by three-dimensionally constructing the inside of a package to enhance a chip containing efficiency.
In the conventional package described above, however, since leads are drawn around in an outer peripheral portion of a semiconductor element, the miniaturization of the package is limited. Furthermore, in the small package such as TSOP and the like, the provision of multiple pins is also limited in respect of the drawing-around of leads and the pin pitch. On the other hand, the resin-sealed type semiconductor device package is requested to be further highly integrated and sophisticated. Accordingly, there are demands for the high heat-release characteristics of the package and the decrease of lead inductance in the package in addition to demands for further multiple pins on the package and the thinning and miniaturizing of the package.